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The Ninth IEEE Workshop on RTL and High Level Testing
(WRTLT08)

November 27-28, 2008
ACU (Advanced Center for Universities)
Sapporo, JAPAN

(To be held in conjunction with ATS'08)

http://aries3a.cse.kyutech.ac.jp/wrtlt08

CALL FOR PARTICIPATION

Scope -- Key Dates -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

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The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. Areas of interest include:

  • High level Testing -- RTL/Behavior level testing, High level approaches for testing, RTL ATPG, RTL DFT, RTL BIST, Synthesis for testability, Relationship between RTL and gate level testing, Functional fault modeling, High level test bench generation
  • SoC Testing -- Test scheduling, Core testing, Interconnect testing, NoC testing
  • Reliable SoC -- System level reliability, Self repair, Fault tolerant SoC
  • Micro Processor Testing         
  • Design Verification(6) Gate Level Test Related Issues -- Low power testing, Test compression, ATPG, DFT, BIST
Key Dates
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Advance registration deadline:  October 24, 2008

Workshop Registration
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Registration forms are now available in PDF and DOC formats on the website.

Advance Program
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This year we set up the theme of "Power/Thermal-Aware Testing", which we believe needs to be discussed not only at gate level but also from high level in this workshop. The following keynote speech, invited talk, and panel discussion on this theme will be scheduled in the afternoon of the first day, November 27.

Keynote Speech: "Power-Aware System-on-Chip Testing" by Erik Larsson, Linkopings University, Sweden

Invited Talk: " Power: The New Dimension of Test" by Patrick Girard, LIRMM, France

Panel: "Roads to Power-Safe LSI Testing" 
Organizer: K. Hatayama, Semiconductor Technology Academic Research Center, Japan 
Moderator: X. Wen, Kyushu Institute of Technology, Japan 

Panelists: 

M. Teheranipoor, University of Connecticut, USA
C. P. Ravikumar, Texas Instruments India, Pvt. Ltd., India
K. Ishibashi, Renesas Technology Corp., Japan
K. Chakravadhanula, Cadence Design Systems, Inc. USA

Twenty three papers in the WRTLT'08 scope will be presented in regular sessions. The advance program will be available by the end of September on our web-site.

More Information
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For further information please visit the website or email wrtlt08@aries30.cse.kyutech.ac.jp.

Committees
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General Chair
Tomoo Inoue, Hiroshima City University

General Vice-Chair
Toshinori Hosokawa, Nihon University

Program Chair
Tsuyoshi Shinogi, Mie University

Finance Chair
Satoshi Ohtake, NAIST

Publicity Chair
Xiaoqing Wen, Kyushu Institute of Technology

Publication Chair
Tomokazu Yoneda, NAIST

Registration Chair
Hiroyuki Yotsuyanagi, Tokushima University

Local Arrangement Chair
Hiroshi Yokoyama, Akita University

Audio Visual Chair
Masayuki Arai, Tokyo Metropolitan University

Secretary
Hideyuki Ichihara, Hiroshima City University

Ex Officio
Hideo Fujiwara , NAIST

Program Committee

Takashi Aikyo, Japan
JiNian Bian, China
Krishnendu Chakrabarty, USA
Tsin-Yuan Chang, Taiwan
Satoshi Fukumoto, Japan
Masaki Hashizume, Japan
Kazumi Hatayama, Japan
Terumine Hayashi, Japan
Yu Hu, China

Michiko Inoue, Japan
Hideo Ito, Japan
Kazuhiko Iwasaki, Japan
Seiji Kajihara, Japan
Erik Larsson, Sweden
Hua-Wei Li, China
Xiao-Wei Li, China
Zainalabedin Navabi, USA
Chia Yee Ooi, Malaysia
Alex Orailoglu, USA
Ilia Polian, Germany
Jaan Raik, Estonia
Kewal K. Saluja, USA
Hideo Tamamoto, Japan
Dong Xiang, China
ZhiQiang You, China
Danella Zhao, USA

Steering Committee

Chair: Xiaowei Li, China
Vice-Chair: Tomoo Inoue, Japan
Members:
  Hideo Fujiwara, Japan
  Terumine Hayashi, Japan
  Kazuhiko Iwasaki, Japan
  Erik Larsson, Sweden
  Alex Orailoglu, USA
  Kewal K. Saluja, USA
  Hideo Tamamoto, Japan
  Dong Xiang, China
  Dafang Zhang, China

For more information, visit us on the web at: http://www.event URL.com

The Ninth IEEE Workshop on RTL and High Level Testing (WRTLT08) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC), and the Technical Group on Dependable Computing, IEICE .


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Doug J. YOUNG
SV Probe Inc.
- USA
Tel.
E-mail dyoung@svprobe.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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